Multi-bit per symbol rate quadrature amplitude encoding

ABSTRACT

In one embodiment, the present invention comprises demultiplexing a bit stream into a first block and a second block, convolutionally coding the first block and block coding the second block. The invention further comprises applying the block coded second block to a function module to apply one of a plurality of different functions to form a third block at an output of the module and mapping the convolutionally coded first block and the third block to a modulation constellation for transmission, the mapping resulting in different constellation points depending on the applied function.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention applies to the field of digital communications systems and, in particular, to flexible bit-rate encoding systems for multi-ary modulation systems.

[0003] 2. Description of the Prior Art

[0004] Presently in transmitting and receiving digital data across noisy channels, it is difficult to find a suitable compromise between adequate bandwidth efficiency and adequate recoverability of the transmitted signal. With high date rates, a signal may not accurately be received, demodulated and recovered. With more modest data rates, the efficiency of the system is reduced. In order to provide a robust communications link, the data rate must be limited. However, in a changing channel, this limit will also change, so that a system that accommodates only a single data rate can not always employ the optimal data rate under the circumstances.

[0005] In some systems, it is possible to vary the bit rate, or symbol rate of signal transmissions, however this often complicates the hardware and software required to implement the system. Other systems permit the modulation scheme to be changed but at still greater cost. The present invention allows the transmitted bit rate to be changed as the quality of the channel changes without significantly complicating the hardware and software. This provides a better combination of error correction coding for the available channel. It is suitable for any kind of digital communications but is particularly suitable for wireless low mobility digital data communications systems.

BRIEF SUMMARY OF THE INVENTION

[0006] In one embodiment, the invention comprises demultiplexing a bit stream into a first block and a second block, convolutionally coding the first block and block coding the second block. The invention further comprises applying the block coded second block to a function module to apply one of a plurality of different functions to form a third block at an output of the module and mapping the convolutionally coded first block and the third block to a modulation constellation for transmission, the mapping resulting in different constellation points depending on the applied function.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0007] The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar elements and in which:

[0008]FIG. 1 is a block diagram illustrating an exemplary architecture of a wireless communication system base station appropriate for use with one embodiment of the present invention;

[0009]FIG. 2 is a block diagram illustrating an exemplary architecture of a wireless communications system remote terminal appropriate for use with the present invention;

[0010]FIG. 3 is block diagram of a codec according to one embodiment of the present invention; and

[0011]FIG. 4 is a diagram of a quadrature amplitude modulation constellation for use in one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0012] Base Station Structure

[0013] The present invention relates to wireless communication systems and may be a fixed-access or mobile-access wireless network using spatial division multiple access (SDMA) technology in combination with multiple access systems, such as time division multiple access (TDMA), frequency division multiple access (FDMA) and code division multiple access (CDMA). Multiple access can be combined with frequency division duplexing (FDD) or time division duplexing (TDD). FIG. 1 shows an example of a base station of a wireless communications system or network suitable for implementing the present invention. The system or network includes a number of subscriber stations, also referred to as remote terminals or user terminals, such as that shown in FIG. 2. The base station may be connected to a wide area network (WAN) through its host DSP 231 for providing any required data services and connections external to the immediate wireless system. To support spatial diversity, a plurality of antennas 103 is used, for example four antennas, although other numbers of antennas may be selected.

[0014] The outputs of the antennas are connected to a duplexer switch 107, which in this TDD system is a time switch. Two possible implementations of switch 107 are as a frequency duplexer in a frequency division duplex (FDD) system, and as a time switch in a time division duplex (TDD) system. When receiving, the antenna outputs are connected via switch 107 to a receiver 205, and are mixed down in analog by RF receiver (“RX”) modules 205 from the carrier frequency to an FM intermediate frequency (“IF”). This signal then is digitized (sampled) by analog to digital converters (“ADCs”) 209. Final down-converting to baseband is carried out digitally. The down-converting can be done using finite impulse response (FIR) filtering techniques. This is shown as block 213. The invention can be adapted to suit a wide variety of RF and IF carrier frequencies and bands.

[0015] There are, in the present example, four down-converted outputs from each antenna's digital filter device 213, one per receive timeslot. The particular number of timeslots can be varied to suit network needs. While the present example uses four uplink and four downlink timeslots for each TDD frame, desirable results have also been achieved with three timeslots for the uplink and downlink in each frame. For each of the four receive timeslots, the four down-converted outputs from the four antennas are fed to a digital signal processor (DSP) device 217 (hereinafter “timeslot processor”) for further processing, including calibration, according to one aspect of this invention. Four Motorola DSP56303 DSPs can be used as timeslot processors, one per receive timeslot. The timeslot processors 217 monitor the received signal power and estimate the frequency offset and time alignment. They also determine smart antenna weights for each antenna element. These are used in the spatial division multiple access scheme to determine a signal from a particular remote user and to demodulate the determined signal.

[0016] The output of the timeslot processors 217 is demodulated burst data for each of the four receive timeslots. This data is sent to the host DSP processor 231 whose main function is to control all elements of the system and interface with the higher level processing, which is the processing which deals with what signals are required for communications in all the different control and service communication channels defined in the system's communication protocol. The host DSP 231 can be a Motorola DSP56303. In addition, timeslot processors send the determined receive weights for each user terminal to the host DSP 231. The host DSP 231 maintains state and timing information, receives uplink burst data from the timeslot processors 217, and programs the timeslot processors 217. In addition it decrypts, descrambles, checks error detecting code, and deconstructs bursts of the uplink signals, then formats the uplink signals to be sent for higher level processing in other parts of the base station. With respect to the other parts of the base station it formats service data and traffic data for further higher processing in the base station, receives downlink messages and traffic data from the other parts of the base station, processes the downlink bursts and formats and sends the downlink bursts to a transmit controller/modulator, shown as 237. The host DSP also manages programming of other components of the base station including the transmit controller/modulator 237 and the RF timing controller shown as 233.

[0017] The RF timing controller 233 interfaces with the RF system, shown as block 245 and also produces a number of timing signals that are used by both the RF system and the modem. The RF controller 233 reads and transmits power monitoring and control values, controls the duplexer 107 and receives timing parameters and other settings for each burst from the host DSP 231.

[0018] The transmit controller/modulator 237, receives transmit data from the host DSP 231, four symbols at a time. The transmit controller uses this data to produce analog IF outputs which are sent to the RF transmitter (TX) modules 245. Specifically, the received data bits are converted into a complex modulated signal, up-converted to an IF frequency, 4-times over-sampled, multiplied by transmit weights obtained from host DSP 231, and converted via digital to analog converters (“DACs”) which are part of transmit controller/modulator 237 to analog transmit waveforms. The analog waveforms are sent to the transmit modules 245.

[0019] The transmit modules 245 up-convert the signals to the transmission frequency and amplify the signals. The amplified transmission signal outputs are sent to antennas 103 via the duplexer/time switch 107.

[0020] User Terminal Structure

[0021]FIG. 2 depicts an example component arrangement in a remote terminal that provides data or voice communication. The remote terminal's antenna 45 is connected to a duplexer 46 to permit antenna 45 to be used for both transmission and reception. The antenna can be omni-directional or directional. For optimal performance, the antenna can be made up of multiple elements and employ spatial processing as discussed above for the base station. In an alternate embodiment, separate receive and transmit antennas are used eliminating the need for the duplexer 46. In another alternate embodiment, where time division duplexing is used, a transmit/receive (TR) switch can be used instead of a duplexer as is well-known in the art. The duplexer output 47 serves as input to a receiver 48. The receiver 48 produces a down-converted signal 49 which is the input to a demodulator 51. A demodulated received sound or voice signal 67 is input to a speaker 66.

[0022] The remote terminal has a corresponding transmit chain in which data or voice to be transmitted is modulated in a modulator 57. The modulated signal to be transmitted 59, output by the modulator 57, is up-converted and amplified by a transmitter 60, producing a transmitter output signal 61. The transmitter output 61 is then input to the duplexer 46 for transmission by the antenna 45.

[0023] The demodulated received data 52 is supplied to a remote terminal central processing unit 68 (CPU) as is received data before demodulation 50. The remote terminal CPU 68 can be implemented with a standard DSP (digital signal processor) device such as a Motorola series 56300 DSP. This DSP can also perform the functions of the demodulator 51 and the modulator 57. The remote terminal CPU 68 controls the receiver through line 63, the transmitter through line 62, the demodulator through line 52 and the modulator through line 58. It also communicates with a keyboard 53 through line 54 and a display 56 through line 55. A microphone 64 and speaker 66 are connected through the modulator 57 and the demodulator 51 through lines 65 and 66, respectively for a voice communications remote terminal. In another embodiment, the microphone and speaker are also in direct communication with the CPU to provide voice or data communications.

[0024] The remote terminal's voice signal to be transmitted 65 from the microphone 64 is input to a modulator 57. Traffic and control data to be transmitted 58 is supplied by the remote terminal's CPU 68. Control data 58 is transmitted to base stations during registration, session initiation and termination as well as during the session as described in greater detail below.

[0025] In an alternate embodiment, the speaker 66, and the microphone 64 are replaced or augmented by digital interfaces well-known in the art that allow data to be transmitted to and from an external data processing device (for example, a computer). In one embodiment, the remote terminal's CPU is coupled to a standard digital interface such as a PCMCIA interface to an external computer and the display, keyboard, microphone and speaker are a part of the external computer. The remote terminal's CPU 68 communicates with these components through the digital interface and the external computer's controller. For data only communications, the microphone and speaker can be deleted. For voice only communications, the keyboard and display can be deleted.

[0026] Signal Modulation

[0027]FIG. 3 shows a block diagram of a signal modulator, corresponding to block 62 of FIG. 1, or block 237 of FIG. 2, according to one embodiment of the present invention. While only the portion related to encoding is shown, the invention is equally applicable to decoding with appropriate reversal of the described steps as is implemented in the signal demodulator 52 of FIG. 1 and as well-known in the art. In one example, the blocks shown in FIG. 3 are implemented in a general purpose DSP (digital signal processor) such as a Motorola 56300 series DSP.

[0028] In one embodiment, the incoming bit stream 310 is processed in variable bit sized blocks. The precise number of bits may be varied here as well as throughout the description to better suit particular applications. In the present invention, a demultiplexer 312 is configurable by a controller module 311 to accept blocks of different sizes in order to support different bit-per-symbol rates at the other end of the modulator. In one example, the input blocks contain either 1458, 1705, or 1952 bits depending on the selected bit-per-symbol rate. These numbers have been chosen because the number of symbols selected for transmission in each downlink time slot of each time division duplex frame has been selected as 494.

[0029] As discussed below, applying the methods of the present invention maps the three different block sizes into 494 symbols. In an exemplary embodiment, 182 symbols has been selected for each uplink slot, accordingly for uplink slots, the input blocks are different than for downlink slots. The uplink slot is not discussed herein in order to simplify the description, however the same principles as applied here to the downlink slot apply also to the uplink slot. The particular selections of symbol rates and input block sizes can be selected to suit the particular application as appropriate. The input block is encrypted and contains some error detecting coding such as a 16-bit cyclic redundancy code in the last 16 bit positions. This encryption and coding is typically performed at earlier stages of physical layer processing by the same general purpose DSP.

[0030] The input block bits are divided roughly in half in the demultiplexer 312 so that roughly one half goes to an upper path 314 and roughly half to a lower path 316. In every case in the present example, the upper path receives 733 bits. The division is done by assigning the initial 733 bits in the input block to the upper path 314 and the remaining bits to the lower path 316. Accordingly, the lower path receives either 725, 972 or 1219 bits depending on the input size block. However, the bits can be divided in any convenient fashion that is reversible in a receive channel.

[0031] The upper path is provided first to a tail bit append block. This block adds eight zero value tail bits to the upper block forming a 741-bit block. The tail append block can be modified or removed altogether, or one value bits may be used depending upon the needs of the particular system. The upper block with the eight appended tail bits is then supplied to a convolutional coder 318.

[0032] In one embodiment, this convolutional coder 318 has 256 states and is of constraint length 9 with 1 message bit per 2 coded bits. The coder is defined by the two generator sequences 561 and 753 (octal) or equivalently 101110001 and 111101011 (binary). The first and second generator sequences define the shift register taps for the first and second encoder output bits, respectively. The coder is initialized to the zero state before each 741 bit block. The outputs of the encoder are concatenated serially, alternating between the two shift register taps of the generator sequences to form a coded output bit stream of 1482 bits. Many other convolutional codes may be used with the present invention to suit particular applications as is well-known in the art. The 1482-bit convolutionally coded blocks are passed next to a puncturer 319.

[0033] In one embodiment, the coded output bit stream is then punctured to delete the fourth and sixth bit from every set of six bits. Accordingly the output encoded bit stream 320 of the convolutional coder is reduced to 988 bits and formed into 247 four-bit blocks. The structure, after puncturing, is c₁c₂c₃c₅, c₇c₈c₉c₁₁, C₁₃C₁₄C₁₅C₁₇, . . . , where c represents a convolutionally coded bit. Other puncturing schemes may also be selected applying techniques well-known in the art. The puncturer may be coupled to the controller 311 so that it can be enabled or disabled or so that the puncturing rate can be modified.

[0034] The punctured upper path is next supplied to an amplitude shift keying mapper 322 which provides I and Q signal lines 334, 336 mapped into a 12, 16 or 24 Quadrature Amplitude Modulation (QAM) constellation to be described in greater detail below.

[0035] The lower output 316 of the demultiplexer 312 is applied to a simple parity coder 324. The parity coder adds sixteen parity bits to the input block to render the blocks into sizes of 741, 988 and 1235 bits respectively. Each parity bit is computed by taking the bit-wise exclusive or (XOR) of a block of 47, 63 or 79 input bits, respectively. The last block of input bits being shorter as appropriate. As an alternative, a Hamming coder or any other kind of block coder could be used depending upon the computational resources available to the system and the needs of the demodulation scheme. Since the parity coding operation in the present embodiment operates on different sized input blocks, the parity coder is shown as being coupled to the controller. The block coder can also be coupled to the controller, if desired, to support different block coding schemes.

[0036] The coded block is passed next to a function module 328 such as a block shaper. The function module, in one embodiment, is a set of block shaping look-up tables that convert the input bits into output sequences. The nature of the table and of the output sequences depends upon the size of the input block and accordingly is set by the controller. The tables are selected to produce an appropriate shaped block for modulation over the communications channel. Alternatively the function module can be a set of software modules that apply one of plurality of different functions to the input bits in order to produce the third block of bits on line 330. The block shaper can also be a set of logic or functional gates in and ASIC or other DSP. The selection of the gates and accordingly, the function that is applied is again determined by the controller 31 1. The output sequences on line 330 are connected as the third block to the ASK mapper 322 which combines this third block output with the upper path bits to provide I and Q signal lines 334, 336 mapped into the QAM constellation.

[0037] In one embodiment, the output of the shaper is a trit, a trinary or base three digit having a value of 0, 1 or 2. Two trits are combined in the ASK mapper with two bits from the upper path to determine a constellation point, i.e. a symbol, in the QAM constellation shown in FIG. 4. The particular nature of the constellation, whether 12-, 16- or 24-QAM, is determined by the mapping function performed by the block shaper 328. A first trit and bit determine the I coordinate in the constellation and the second trit and second bit determine the Q coordinate. Table 1 shows a mapping structure that can be used by the ASK mapper. The coordinate is the value on the I or Q axis as shown on FIG. 4.

[0038] As can be seen from Table 1, the trit determines the amplitude of the modulation, i.e. the distance along the axis from the origin. The bit determines the sign of the magnitude, i.e. the sector in FIG. 4 for the point. This distinction aids in the demodulation of the symbols by the receiver. Alternatively, the relationship can be switched, or a different relationship can be used. While trit, bit combinations are used in the present description for clarity, equivalent binary values can be substituted for the trits. As is well-known in the art, the base of the numbering system, whether binary, trinary, decimal, hexadecimal or any other system can be selected to best suit the particular implementation involved. TABLE 1 Trit 2 1 0 0 1 2 Bit 0 1 0 1 0 1 Coordinate −5 −3 −1 1 3 5

[0039]FIG. 4 shows an exemplary 36-ary QAM constellation. The constellation has an I (in-phase) axis 402 and an orthogonal Q (quadrature) axis 404. Each of the 36 constellation points are aligned with values of ±1, ±3 or ±5 on the coordinate axes, as is well-known in the art. The values on the I and Q axes correspond to the “Coordinate” row shown in Table 1 above. As Table 1 shows, each point is associated with a trit, bit combination from 00 to 21 and has corresponding I and Q coordinates. While, in the present embodiment, the symbols are mapped directly to the corresponding points on the I,Q axes, this is not required. A variety of alternative mapping approaches may be used. Alternatively, binary values can be mapped to every other or every third or fourth point around the constellation in order to obtain a more desirable distribution of symbols for transmission. Alternatively, other constellations may be used instead of the rectangular constellation shown in FIG. 4 such as circular, triangular and hexagonal constellations. In addition while multi-ary QAM constellations are shown in the illustrated embodiments other multi-ary transmission technologies such as phase shift keying (PSK) or frequency shift keying (FSK) can be employed instead.

[0040] The block shaper uses different tables to form the trits depending on the size of the input block. A suitable table in one embodiment for the smallest block, the 741-bit block, is as shown below in Table 2. This table considers three bits at a time and produces an output of four trits for every three bits. In this table, the trinary digit of value 2 is not used, so the output trits appear to be four binary digits but they are considered as trits by the ASK mapper. These tits can be represented as binary numbers in software or hardware which is developed to implement the present invention. Variations on the table can be made to meet different system demands. The table below preserves parity from input to output and minimizes the trit values, 2 is not used and 1 is used minimally. Since the mapping scheme in Table 1 above assigns trits of 2 and 1 to higher power levels in the QAM constellation, minimizing the use of 2 and 1 reduces the average power of the transmitted signal. TABLE 2 Bits in  000  001  010  011  100  101  110  111 Trits 0000 0001 0010 0101 0100 0110 1010 1000

[0041] Referring to FIG. 4, it can be seen that if the trits of Table 2 are applied against the mapping of Table 1 only a small number of the possible constellation points will be mapped. These points are enclosed by a solid line 406 and shown as circles with cross hairs 408 in FIG. 4 and create a 12-ary constellation. In the two pairs of output trits of Table 2, 1's do not occur consecutively in the first pair or in the second pair. As a result, from Table 1, the corner points of coordinates (±3, ±3) will not be used, thereby avoiding the higher power required for these points as compared to the points that lie closer to the origin. These corner points are shown as squares 412 in FIG. 4.

[0042] For the larger 988-bit block, a different table is used, as selected by the controller. This table maps each set of four input bits directly into four output trits. Each input binary digit is identical to each output trinary digit. As in Table 2, parity is preserved and the trinary digit 2 is avoided completely. Referring again to Table 1, the possible constellation points are those enclosed within the dashed line 410. This includes the points 408 of the 12-ary constellation and the corner points 412 shown as squares in FIG. 4. Any constellation point with a coordinate on either axis of ±5 is avoided, limiting the average power of the modulated signal. These points are shown as triangles 416 and crosses 418 in FIG. 4. The possible points make up a conventional 16-ary QAM constellation. TABLE 3 Bits in 0000 0001 0010 0011 0100 0101 0110 0111 Tilts 0000 0001 0010 0011 0100 0101 0110 0111 Bits in 1000 1001 1010 1011 1100 1101 1110 1111 Tilts 1000 1001 1010 1011 1100 1101 1110 1111

[0043] For the largest input block, the 1235-bit input block, a third table is used. This table maps five input bits into four output trits. The 32 columns of the table can be represented as shown in Table 4 below. In the table, i2 refers to the second input bit, whether 0 or 1. i3, i4 and i5 correspondingly refer to the third, fourth and fifth input bits, respectively. 1-i5 refers to the binary complement of the fifth input bit, i.e. if i5 is 0, then 1-i5 is 1 and if i5 is 1, then 1-i5 is 0. This table, like Tables 2 and 3 preserves parity between the input and the output, where the trit values of 1 and 2 are taken to have the same parity. Table 4 also features few 2's and 1's, accordingly reducing the power required to transmit the symbols as discussed above. TABLE 4 Bits in 0 i2 i3 i4 i5 1 0 0 i4 i5 1 0 1 i4 i5 1 1 0 i4 i5 1 1 1 i4 i5 Trits i2 i3 i4 i5 2 0 i4 i5 0 2 i4 1-i5 i4 1-i5 2 0 i4 i5 0 2

[0044] Referring again to Table 1 and the constellation of FIG. 4. The trits are combined in pairs with pairs of bits to generate a constellation point. The trit 2 invokes a coordinate of ±5 on one of the axes. Since in Table 4 there is no pair of output trits of 2,2, the extreme corners of the 36-ary constellation of FIG. 4 will not be used by the ASK mapper. Further since there is no trit pair containing 2 and 1, e.g. (2,1) and (1,2), the points with coordinates (±3, ±5) and (±5, ±3) are also avoided. These points are marked with crosses 418 in FIG. 4. The remaining points that are possible symbols for the largest input block are enclosed by the dotted line 414 in FIG. 4 and constitute a 24-ary QAM constellation.

[0045] As can be seen from the discussion above, for each bit-per-symbol rate, the ASK mapper takes 988 bits and 988 trits, combines them and maps them into 494 symbols in a 12-, 16-, or 24-ary QAM constellation. The symbols are built using the lower line 330 from the block shaper 328 as the most significant trit and the upper convolutional coded line 320 as the least significant bit, however, the bits may be combined in any other way. Any one input block to the demultiplexer 312 on the main input line 310 will accordingly be mapped into 494 consecutive symbols. These are presented as I and Q coordinates on the I and Q lines 334, 336 for transmission over the channel as is well-known in the art. In the system architecture of FIG. 1, the QAM constellation is modulated onto the appropriate carrier and transmitted through antennas 103 or the antenna of the remote terminal 45.

[0046] As mentioned above, the size of the blocks input to the system can be varied in order to accommodate different system requirements. While three examples have been set forth herein, many more possibilities can be developed as is well-known in the art. As can be seen from the specific examples provided above, the present invention converts a 1458-bit, 1705-bit or 1952-bit block into two 494-bit or trit blocks that are mapped into 494 symbols. Accordingly, the system provides alternatives of roughly 3, 3½, and 4 bits per symbol. These different rates provides flexibility to accommodate channels of varying quality. Further variations in bit rates can be added, employing the teachings of the present invention in several ways. Further tables can be added to the block shaper to support further bit rate mappings. This might permit quaternary, 32-ary and 36-ary QAM, for example, as shown in FIG. 4. The puncture rate may be varied and the number of tail bits appended to the upper line may be varied. The type of block code can also be varied to suit different bit rates and puncturing can be added to the lower line.

[0047] In the description above, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.

[0048] The present invention includes various steps. The steps of the present invention may be performed by hardware components, such as those shown in FIGS. 1 and 2, or may be embodied in machine-executable instructions, which may be used to cause a general-purpose or special-purpose processor or logic circuits programmed with the instructions to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software. The steps have been described as being performed by either the base station or the user terminal. However, any steps described as being performed by the base station may be performed by the user terminal and vice versa. The invention is equally applicable to systems in which terminals communicate with each other without either one being designated as a base station, a user terminal, a remote terminal or a subscriber station.

[0049] The present invention may be provided as a computer program product which may include a machine-readable medium having stored thereon instructions which may be used to program a computer (or other electronic devices) to perform a process according to the present invention. The machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, magnet or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing electronic instructions. Moreover, the present invention may also be downloaded as a computer program product, wherein the program may be transferred from a remote computer to a requesting computer by way of data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a modem or network connection).

[0050] Importantly, while the present invention has been described in the context of a wireless internet data system for portable handsets, it can be applied to a wide variety of different wireless systems in which data are exchanged. Such systems include voice, video, music, broadcast and other types of data systems without external connections. The present invention can be applied to fixed remote terminals as well as to low and high mobility terminals. Many of the methods are described in their most basic form but steps can be added to or deleted from any of the methods and information can be added or subtracted from any of the described messages without departing from the basic scope of the present invention. It will be apparent to those skilled in the art that many further modifications and adaptations can be made. The particular embodiments are not provided to limit the invention but to illustrate it. The scope of the present invention is not to be determined by the specific examples provided above but only by the claims below. 

What is claimed is:
 1. A method comprising: demultiplexing a bit stream into a first block and a second block; convolutionally coding the first block; block coding the second block; applying the block coded second block to a function module to apply one of a plurality of different functions to form a third block at an output of the module; mapping the convolutionally coded first block and the third block to a modulation constellation for transmission, the mapping resulting in different constellation points depending on the applied function.
 2. The method of claim 1 wherein applying one of a plurality of different functions comprises applying one of a plurality of different look-up tables, the look-up tables containing alternative portions of the third block.
 3. The method of claim 2 wherein the plurality of look-up tables each receive a different number of bits and wherein the third block comprises a shaped block that has a number of digits that is the same for all look-up tables.
 4. The method of claim 1 wherein the third block is shaped to optimize transmission over a communications channel.
 5. The method of claim 1 wherein the block-coded second block is the same as the third block.
 6. The method of claim 1 wherein applying comprises receiving a differing number of bits depending upon the applied function and wherein forming a third block comprises forming a shaped block that has a number of digits that is the same for all functions.
 7. The method of claim 1 wherein forming a third block comprises forming a third block that is represented as a base 3 digit.
 8. The method of claim 7 wherein the number of base 3 digits in the third block equals the number of digits in the convolutionally encoded second block.
 9. The method of claim 1 wherein the modulation constellation comprises a phase shift keyed constellation.
 10. The method of claim 1 wherein mapping comprises mapping into different sets of constellation points depending on the applied function, the different sets of constellation points having different numbers of constellation points.
 11. The method of claim 10 wherein the different sets of constellation points correspond to different bit-per-symbol rates, based on the demultiplexed bitstream.
 12. The method of claim 1 wherein mapping comprises mapping the position of a coordinate within a sector in the constellation based on one of either the convolutionally coded first block and the third block.
 13. The method of claim 12 wherein mapping comprises mapping the sign of a coordinate in the constellation based on the other of either the convolutionally coded first block and the shaped block in combination with the mapped coordinate within a sector.
 14. The method of claim 1 wherein the block code comprises a parity code.
 15. The method of claim 14 wherein the function module preserves the parity of the block coded second block in forming the third block.
 16. The method of claim 1 further comprising appending a set of tail bits to the first block before convolutionally coding.
 17. The method of claim 1 wherein demultiplexing comprises demultiplexing a differing proportion of bits to the first and second blocks based on the one of the plurality of functions applied.
 18. A machine-readable medium having stored thereon data representing sequences of instructions which, when executed by a machine, cause the machine to perform operations comprising: demultiplexing a bit stream into a first block and a second block; convolutionally coding the first block; block coding the second block; applying the block coded second block to a function module to apply one of a plurality of different functions to form a third block at an output of the module; mapping the convolutionally coded first block and the third block to a modulation constellation for transmission, the mapping resulting in different constellation points depending on the applied function.
 19. The medium of claim 18 wherein the instructions causing the machine to perform operations comprising applying one of a plurality of different functions further comprise instructions causing the machine to perform operations comprising applying one of a plurality of different look-up tables, the look-up tables containing alternative portions of the third block.
 20. The medium of claim 19 wherein the plurality of look-up tables each receive a different number of bits and wherein the third block comprises a shaped block that has a number of digits that is the same for all look-up tables.
 21. The medium of claim 18 wherein the instructions causing the machine to perform operations comprising applying further comprise instructions causing the machine to perform operations comprising receiving a differing number of bits depending upon the applied function and wherein the instructions causing the machine to perform operations comprising forming a third block further comprise instructions causing the machine to perform operations comprising forming a shaped block that has a number of digits that is the same for all functions.
 22. The medium of claim 18 wherein the instructions causing the machine to perform operations comprising mapping further comprise instructions causing the machine to perform operations comprising mapping into different sets of constellation points depending on the applied function, the different sets of constellation points having different numbers of constellation points.
 23. The medium of claim 18 wherein the instructions causing the machine to perform operations comprising mapping further comprise instructions causing the machine to perform operations comprising mapping the position of a coordinate within a sector in the constellation based on one of either the convolutionally coded first block and the third block.
 24. The medium of claim 23 wherein the instructions causing the machine to perform operations comprising mapping further comprise instructions causing the machine to perform operations comprising mapping the sign of a coordinate in the constellation based on the other of either the convolutionally coded first block and the shaped block in combination with the mapped coordinate within a sector.
 25. An apparatus: a demultiplexer to divide a bit stream into a first block and a second block; a convolutional coder coupled to the demultiplexer to receive and encode the first block; a block coder coupled to the demultiplexer to receive and encode the second block; a function module coupled to the block coder to receive the block coded second block and apply one of a plurality of different functions to form a third block at an output of the module; a mapper to map the convolutionally coded first block and the third block to a modulation constellation for transmission, the mapping resulting in different constellation points depending on the applied function; and a controller coupled to the demultiplexer to control the size of the first and second blocks and to the function module to control which of the plurality of functions to apply.
 26. The apparatus of claim 25 wherein the function module comprises a plurality of different look-up tables, the look-up tables containing alternative portions of the third block.
 27. The apparatus of claim 26 wherein the plurality of look-up tables each receive a different number of bits and wherein the third block comprises a shaped block that has a number of digits that is the same for all look-up tables.
 28. The apparatus of claim 25 wherein the mapper maps into different sets of constellation points depending on the applied function, the different sets of constellation points having different numbers of constellation points.
 29. The method of claim 1 wherein the block code comprises a parity code and wherein the function module preserves the parity of the block coded second block in forming the third block. 